Timing Report

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Design Name MSX_SRAM_mapper_512K
Device, Speed (SpeedFile Version) XC9536, -7 (3.0)
Date Created Thu Dec 9 08:16:39 2010
Created By Timing Report Generator: version M.53d
Copyright Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'fc_bit0.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fc_bit1.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fc_bit2.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fc_bit3.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fc_bit4.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fd_bit0.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fd_bit1.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fd_bit2.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fd_bit3.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fd_bit4.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fe_bit0.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fe_bit1.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fe_bit2.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fe_bit3.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'fe_bit4.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'ff_bit0.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'ff_bit1.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'ff_bit2.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'ff_bit3.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.
Possible asynchronous logic: Clock pin 'ff_bit4.CLKF' has multiple original clock nets 'IORQ' 'WR' 'a0' 'a1'.

Performance Summary
Min. Clock Period 20.000 ns.
Max. Clock Frequency (fSYSTEM) 50.000 MHz.
Limited by Cycle Time for IORQ
Clock to Setup (tCYC) 20.000 ns.
Pad to Pad Delay (tPD) 15.500 ns.
Setup to Clock at the Pad (tSU) -10.000 ns.
Clock Pad to Output Pad Delay (tCO) 45.500 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
AUTO_TS_F2F 0.0 20.0 20 20
AUTO_TS_P2P 0.0 45.5 108 108
AUTO_TS_P2F 0.0 24.0 220 220
AUTO_TS_F2P 0.0 21.5 40 40


Constraint: TS1000

Description: PERIOD:PERIOD_IORQ:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_WR:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_a0:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_a1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
fc_bit0.Q to fc_bit0.D 0.000 20.000 -20.000
fc_bit1.Q to fc_bit1.D 0.000 20.000 -20.000
fc_bit2.Q to fc_bit2.D 0.000 20.000 -20.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
IORQ to d0 0.000 45.500 -45.500
IORQ to d1 0.000 45.500 -45.500
IORQ to d2 0.000 45.500 -45.500


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
IORQ to fc_bit0.CLKF 0.000 24.000 -24.000
IORQ to fc_bit1.CLKF 0.000 24.000 -24.000
IORQ to fc_bit2.CLKF 0.000 24.000 -24.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
fc_bit0.Q to d0 0.000 21.500 -21.500
fc_bit0.Q to ma14 0.000 21.500 -21.500
fc_bit1.Q to d1 0.000 21.500 -21.500



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
IORQ 50.000 Limited by Cycle Time for IORQ
WR 50.000 Limited by Cycle Time for WR
a0 50.000 Limited by Cycle Time for a0
a1 50.000 Limited by Cycle Time for a1

Setup/Hold Times for Clocks

Setup/Hold Times for Clock IORQ
Source Pad Setup to clk (edge) Hold to clk (edge)
a2 -10.000 13.000
a3 -10.000 13.000
a4 -10.000 13.000
a5 -10.000 13.000
a6 -10.000 13.000
a7 -10.000 13.000
d0 -10.000 13.000
d1 -10.000 13.000
d2 -10.000 13.000
d3 -10.000 13.000
d4 -10.000 13.000

Setup/Hold Times for Clock WR
Source Pad Setup to clk (edge) Hold to clk (edge)
a2 -10.000 13.000
a3 -10.000 13.000
a4 -10.000 13.000
a5 -10.000 13.000
a6 -10.000 13.000
a7 -10.000 13.000
d0 -10.000 13.000
d1 -10.000 13.000
d2 -10.000 13.000
d3 -10.000 13.000
d4 -10.000 13.000

Setup/Hold Times for Clock a0
Source Pad Setup to clk (edge) Hold to clk (edge)
a2 -10.000 13.000
a3 -10.000 13.000
a4 -10.000 13.000
a5 -10.000 13.000
a6 -10.000 13.000
a7 -10.000 13.000
d0 -10.000 13.000
d1 -10.000 13.000
d2 -10.000 13.000
d3 -10.000 13.000
d4 -10.000 13.000

Setup/Hold Times for Clock a1
Source Pad Setup to clk (edge) Hold to clk (edge)
a2 -10.000 13.000
a3 -10.000 13.000
a4 -10.000 13.000
a5 -10.000 13.000
a6 -10.000 13.000
a7 -10.000 13.000
d0 -10.000 13.000
d1 -10.000 13.000
d2 -10.000 13.000
d3 -10.000 13.000
d4 -10.000 13.000


Clock to Pad Timing

Clock IORQ to Pad
Destination Pad Clock (edge) to Pad
d0 45.500
d1 45.500
d2 45.500
d3 45.500
d4 45.500
ma14 45.500
ma15 45.500
ma16 45.500
ma17 45.500
ma18 45.500

Clock WR to Pad
Destination Pad Clock (edge) to Pad
d0 45.500
d1 45.500
d2 45.500
d3 45.500
d4 45.500
ma14 45.500
ma15 45.500
ma16 45.500
ma17 45.500
ma18 45.500

Clock a0 to Pad
Destination Pad Clock (edge) to Pad
d0 45.500
d1 45.500
d2 45.500
d3 45.500
d4 45.500
ma14 45.500
ma15 45.500
ma16 45.500
ma17 45.500
ma18 45.500

Clock a1 to Pad
Destination Pad Clock (edge) to Pad
d0 45.500
d1 45.500
d2 45.500
d3 45.500
d4 45.500
ma14 45.500
ma15 45.500
ma16 45.500
ma17 45.500
ma18 45.500


Clock to Setup Times for Clocks

Clock to Setup for clock IORQ
Source Destination Delay
fc_bit0.Q fc_bit0.D 20.000
fc_bit1.Q fc_bit1.D 20.000
fc_bit2.Q fc_bit2.D 20.000
fc_bit3.Q fc_bit3.D 20.000
fc_bit4.Q fc_bit4.D 20.000
fd_bit0.Q fd_bit0.D 20.000
fd_bit1.Q fd_bit1.D 20.000
fd_bit2.Q fd_bit2.D 20.000
fd_bit3.Q fd_bit3.D 20.000
fd_bit4.Q fd_bit4.D 20.000
fe_bit0.Q fe_bit0.D 20.000
fe_bit1.Q fe_bit1.D 20.000
fe_bit2.Q fe_bit2.D 20.000
fe_bit3.Q fe_bit3.D 20.000
fe_bit4.Q fe_bit4.D 20.000
ff_bit0.Q ff_bit0.D 20.000
ff_bit1.Q ff_bit1.D 20.000
ff_bit2.Q ff_bit2.D 20.000
ff_bit3.Q ff_bit3.D 20.000
ff_bit4.Q ff_bit4.D 20.000

Clock to Setup for clock WR
Source Destination Delay
fc_bit0.Q fc_bit0.D 20.000
fc_bit1.Q fc_bit1.D 20.000
fc_bit2.Q fc_bit2.D 20.000
fc_bit3.Q fc_bit3.D 20.000
fc_bit4.Q fc_bit4.D 20.000
fd_bit0.Q fd_bit0.D 20.000
fd_bit1.Q fd_bit1.D 20.000
fd_bit2.Q fd_bit2.D 20.000
fd_bit3.Q fd_bit3.D 20.000
fd_bit4.Q fd_bit4.D 20.000
fe_bit0.Q fe_bit0.D 20.000
fe_bit1.Q fe_bit1.D 20.000
fe_bit2.Q fe_bit2.D 20.000
fe_bit3.Q fe_bit3.D 20.000
fe_bit4.Q fe_bit4.D 20.000
ff_bit0.Q ff_bit0.D 20.000
ff_bit1.Q ff_bit1.D 20.000
ff_bit2.Q ff_bit2.D 20.000
ff_bit3.Q ff_bit3.D 20.000
ff_bit4.Q ff_bit4.D 20.000

Clock to Setup for clock a0
Source Destination Delay
fc_bit0.Q fc_bit0.D 20.000
fc_bit1.Q fc_bit1.D 20.000
fc_bit2.Q fc_bit2.D 20.000
fc_bit3.Q fc_bit3.D 20.000
fc_bit4.Q fc_bit4.D 20.000
fd_bit0.Q fd_bit0.D 20.000
fd_bit1.Q fd_bit1.D 20.000
fd_bit2.Q fd_bit2.D 20.000
fd_bit3.Q fd_bit3.D 20.000
fd_bit4.Q fd_bit4.D 20.000
fe_bit0.Q fe_bit0.D 20.000
fe_bit1.Q fe_bit1.D 20.000
fe_bit2.Q fe_bit2.D 20.000
fe_bit3.Q fe_bit3.D 20.000
fe_bit4.Q fe_bit4.D 20.000
ff_bit0.Q ff_bit0.D 20.000
ff_bit1.Q ff_bit1.D 20.000
ff_bit2.Q ff_bit2.D 20.000
ff_bit3.Q ff_bit3.D 20.000
ff_bit4.Q ff_bit4.D 20.000

Clock to Setup for clock a1
Source Destination Delay
fc_bit0.Q fc_bit0.D 20.000
fc_bit1.Q fc_bit1.D 20.000
fc_bit2.Q fc_bit2.D 20.000
fc_bit3.Q fc_bit3.D 20.000
fc_bit4.Q fc_bit4.D 20.000
fd_bit0.Q fd_bit0.D 20.000
fd_bit1.Q fd_bit1.D 20.000
fd_bit2.Q fd_bit2.D 20.000
fd_bit3.Q fd_bit3.D 20.000
fd_bit4.Q fd_bit4.D 20.000
fe_bit0.Q fe_bit0.D 20.000
fe_bit1.Q fe_bit1.D 20.000
fe_bit2.Q fe_bit2.D 20.000
fe_bit3.Q fe_bit3.D 20.000
fe_bit4.Q fe_bit4.D 20.000
ff_bit0.Q ff_bit0.D 20.000
ff_bit1.Q ff_bit1.D 20.000
ff_bit2.Q ff_bit2.D 20.000
ff_bit3.Q ff_bit3.D 20.000
ff_bit4.Q ff_bit4.D 20.000


Pad to Pad List

Source Pad Destination Pad Delay
IORQ Busdir 15.500
RD Busdir 15.500
a0 d0 15.500
a0 d1 15.500
a0 d2 15.500
a0 d3 15.500
a0 d4 15.500
a1 d0 15.500
a1 d1 15.500
a1 d2 15.500
a1 d3 15.500
a1 d4 15.500
a14 ma14 15.500
a14 ma15 15.500
a14 ma16 15.500
a14 ma17 15.500
a14 ma18 15.500
a15 ma14 15.500
a15 ma15 15.500
a15 ma16 15.500
a15 ma17 15.500
a15 ma18 15.500
a2 Busdir 15.500
a3 Busdir 15.500
a4 Busdir 15.500
a5 Busdir 15.500
a6 Busdir 15.500
a7 Busdir 15.500
IORQ d0 9.500
IORQ d1 9.500
IORQ d2 9.500
IORQ d3 9.500
IORQ d4 9.500
RD d0 9.500
RD d1 9.500
RD d2 9.500
RD d3 9.500
RD d4 9.500
a2 d0 9.500
a2 d1 9.500
a2 d2 9.500
a2 d3 9.500
a2 d4 9.500
a3 d0 9.500
a3 d1 9.500
a3 d2 9.500
a3 d3 9.500
a3 d4 9.500
a4 d0 9.500
a4 d1 9.500
a4 d2 9.500
a4 d3 9.500
a4 d4 9.500
a5 d0 9.500
a5 d1 9.500
a5 d2 9.500
a5 d3 9.500
a5 d4 9.500
a6 d0 9.500
a6 d1 9.500
a6 d2 9.500
a6 d3 9.500
a6 d4 9.500
a7 d0 9.500
a7 d1 9.500
a7 d2 9.500
a7 d3 9.500
a7 d4 9.500


Number of paths analyzed: 388
Number of Timing errors: 388
Analysis Completed: Thu Dec 9 08:16:40 2010